Clojars

Clojars

com.github.m1kal/charbel

Write synthesizable FPGA code with Clojure syntax. The code is translated to SystemVerilog.

Leiningen/Boot

[com.github.m1kal/charbel "0.1.7"]

Clojure CLI/deps.edn

com.github.m1kal/charbel {:mvn/version "0.1.7"}

Gradle

implementation("com.github.m1kal:charbel:0.1.7")

Maven

<dependency>
  <groupId>com.github.m1kal</groupId>
  <artifactId>charbel</artifactId>
  <version>0.1.7</version>
</dependency>